John VerWey is a Non-Resident Research Fellow at Georgetown’s Center for Security and Emerging Technology (CSET). Additionally, he is an East Asia National Security Advisor at the U.S. Department of Energy’s Pacific Northwest National Laboratory. At PNNL, John focuses on critical technology protection, export controls, supply chain security, and nonproliferation in the context of U.S.-China technology competition. He is also a non-resident fellow at The National Bureau of Asian Research. Previously, John served in several roles at the Office of the U.S. Trade Representative (USTR), the U.S. International Trade Commission (USITC) and the U.S. Department of Commerce. He was a staff liaison to the Committee on Foreign Investment in the United States (CFIUS) at USTR and supported investigations for the executive branch and congressional committees on economic competitiveness issues at the USITC and Commerce. Prior to federal government service, he consulted for The European Parliament’s Internal Market and Consumer Protection Committee and worked as a program manager at the American Enterprise Institute.
John’s research has been published by the USITC, the Journal of International Commerce and Economics, IEEE-Computer, and CSET, among others, and he has testified before the U.S.-China Economic and Security Review Commission. He holds an MSc in international political economy from the London School of Economics and B.A.s in Asian studies and history from Gonzaga University.
The U.S. semiconductor supply chain’s resilience will meaningfully increase only if current efforts to re-shore fabrication (that is, to situate more facilities that make its key parts in the United States) are met with commensurate efforts to re-shore upstream material production along with downstream assembly, test, and packaging (ATP) of finished microelectronics.
In this condensed version of his June 2022 report, written for Semiconductor Digest, John VerWey outlines how targeted investment incentives to increase U.S.-based advanced packaging capacity are also important for increasing semiconductor supply chain resilience.
The semiconductor industry and the U.S. government are engaged in ambitious plans to expand domestic semiconductor manufacturing capacity. Previous CSET research has found that the CHIPS for America Act incentives, if carefully targeted and augmented by adequate regulatory and workforce support, could reverse the observable decline in U.S. semiconductor manufacturing capacity since 1990. This paper argues that targeted investment incentives to increase U.S.-based advanced packaging capacity are also important for innovation, supply chain security, and ongoing semiconductor industry leadership.
Congress has advanced legislation to appropriate $52 billion in funding for the CHIPS for America Act, which aims to increase semiconductor manufacturing and supply chain resilience in the United States. But more can be done to improve the resiliency of U.S. access to microelectronics beyond manufacturing incentives. This report outlines infrastructure investments and regulatory reforms that could make the United States a more attractive place to build new chipmaking capacity and ensure continued U.S. access to key inputs for semiconductor manufacturing.
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